Product Summary

The XC2S150-5PQG208C Field-Programmable Gate Array gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S150-5PQG208C offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect of XC2S150-5PQG208C means that successive design iterations continue to meet timing requirements.

Parametrics

XC2S150-5PQG208C absolute maximum ratings: (1)Supply voltage relative to GND: –0.5 to 3.0 V; (2)Supply voltage relative to GND: –0.5 to 4.0 V; (3)Input reference voltage: –0.5 to 3.6 V; (4)VIN Input voltage relative to GND: –0.5 to 5.5 V at 5V tolerant I/O, –0.5 to VCCO+0.5 V at No 5V tolerance; (5)Voltage applied to 3-state output: –0.5 to 5.5 V at 5V tolerant I/O, –0.5 to VCCO+0.5 V at No 5V tolerance; (6)Storage temperature (ambient): –65 to +150 ℃; (7)Junction temperature: +125 ℃.

Features

XC2S150-5PQG208C features: (1)Second generation ASIC replacement technology: Densities as high as 5,292 logic cells with up to 200,000 system gates, Streamlined features based on Virtex FPGA architecture, Unlimited reprogrammability, Very low cost, Cost-effective 0.18 micron process; (2)System level features: SelectRAM hierarchical memory: 16 bits/LUT distributed RAM, Configurable 4K bit block RAM, Fast interfaces to external RAM, Fully PCI compliant, Low-power segmented routing architecture.

Diagrams

XC2S150-5PQG208C block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
Quantity
XC2S150-5PQG208C
XC2S150-5PQG208C


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Data Sheet

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