Product Summary

The EP20K100EBC356-2 is the first PLD, which is designed with the MultiCore architecture. It combines the strengths of LUT-based and productterm-based devices with an enhanced memory structure. LUT-based logic of the EP20K100EBC356-2 provides optimized performance and efficiency for data-path, registerintensive, mathematical, or digital signal processing (DSP) designs.

Parametrics

EP20K100EBC356-2 absolute maximum ratings: (1)Supply voltage: –0.5 to 3.6 V With respect to ground; (2)DC input voltage: –2.0 to 5.75 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias: –65 to 150 ℃; (5)Ambient temperature Under bias: –65 to 135 ℃; (6)Junction temperature PQFP, RQFP, TQFP, and BGA packages, under bias: 135 ℃, Ceramic PGA packages, under bias: 150 ℃.

Features

EP20K100EBC356-2 features: (1)MultiCore architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory; (2)LUT logic used for register-intensive functions; (3)Embedded system block (ESB) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM); (4)ESB implementation of product-term logic used for combinatorial-intensive functions.

Diagrams

EP20K100EBC356-2 block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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EP20K100EBC356-2
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